CRAM Model
A simple complexity Model for modern Network Processors
Our goal is to create new Network Algorithms (sometimes called Network Algorithmics) for various tasks (such as IP lookup, packet lookup, security lookups) on modern router chips which contain fine-grained Content-Addressable Memory (CAM) and random-access memory (RAM) that can be dynamically allocated to a set of programmable processors. We target newer network processors such as Intel’s Tofino-1 and 2 (used by the Arista 7170 and Cisco Nexus 34180YC), AMD’s Pensando and NVIDIA’s Bluefield.
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A secondary goal is to create and validate a mathematical model of these processors that we call the CRAM model, akin to famous earlier models of complexity like the RAM and parallel random-access machine (PRAM) models) that allows quickly designing and evaluating scalable algorithms for all router processing tasks. This is helpful because designing algorithms for modern networking chips is challenging because of the need to account for hardware-level details such as pipeline stages, registers and memory limits.
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Our initial work in this space introduces the CRAM Model and applies it to IP Lookup and was published in NSDI 2025
